A semiconductor memory device may receive clock signals having different frequencies. Internal circuits of the semiconductor memory device may not show a same performance for all frequencies and may thus need to perform operations depending on a frequency of an input clock signal. For example, a delay locked loop (DLL) may be used to generate an internal clock signal which is synchronized with a clock signal input from an external portion. In this case, the internal clock signal can be synchronized with the external clock signal even though a delay circuit having a short delay time is used if a frequency of the external clock signal is high. When a frequency of the external clock signal is low, however, the internal clock signal may be synchronized with the external clock signal only if a delay circuit having a relatively long delay time is used. An awareness of a frequency information of the input clock signal may be used to improve frequency characteristics of the internal circuits of the semiconductor memory device.
A conventional semiconductor memory device may use a CL (CAS latency) value set by a user as frequency information for a clock signal. FIG. 1 is a block diagram illustrating a circuit used when different delays are used according to a frequency of a clock signal in a conventional semiconductor memory device. Functions and operations of components of FIG. 1 are explained below.
One of a first delay circuit 10 and a second delay circuit 20 is selected according to a CL value, and an output signal OUT is generated by delaying an input signal IN by a predetermined time period. That is, in a conventional semiconductor memory device, a CL value is set differently according to a frequency of the input clock signal, and a generation time point of internally generated signals depends on a frequency of the input clock signal. Therefore, if a user sets a CL value according to a frequency of a clock signal to be used, the circuit of FIG. 1 selects the first delay circuit 10 or the second delay circuit 12 according to the CL value to make a generation time point of the output signal OUT.
FIG. 2 is a block diagram illustrating a method of adjusting a delay time of a delay circuit according to a frequency of an externally input clock signal in the delay locked loop (DLL) of the conventional semiconductor memory device. In FIG. 2, a third delay circuit 20 and a fourth delay circuit 22 may each have multiple different delay circuits.
A delay locked loop (DLL) may be used to synchronize an internal clock signal with an external clock signal in a semiconductor memory device. As described above, if a delay locked loop is used in a semiconductor memory device, the internal clock signal can be synchronized with the external clock signal even though a delay circuit having a short delay time is used when a frequency of the external clock signal is high. In contrast, a delay circuit having a relatively long delay time may be needed when a frequency of the external clock signal is low. The semiconductor memory device of FIG. 2 generates a relatively short delay time period by cutting a second fuse 24 using a CL value set by a user for the third delay circuit 20 to generate the internal clock signal and for the fourth delay circuit 22 to not operate when a frequency of a clock signal is high. The semiconductor memory device of FIG. 2 generates a relatively long delay time period such that the internal clock signal is generated through both the third delay circuit 20 and the fourth delay circuit 22 without cutting the first and second fuses 24 and 26.
If a CL value is used as frequency information for a clock signal, however, there may be a problem in that a user should change a CL value whenever a frequency of a clock signal input to the semiconductor memory device is varied. The semiconductor memory device may operate abnormally if a user makes a mistake in setting a CL value.